A data-communications system, such as a computer disk drive or a cell phone, typically includes a read channel, which recovers data from a received read signal (sometimes called a data signal) by synchronizing a read-signal sample clock to the read signal and by controlling the read-channel gain to impart a predetermined amplitude to the read signal.
The read signal often includes a preamble, which precedes the data and which facilitates the synchronizing of the sample clock and the controlling of the channel gain.
An analog-synchronizing data-communications system shifts the phase and frequency of the sample clock to respectively match the phase and frequency of the data that the read signal is carrying. But shifting the phase and/or frequency of the sample clock may generate harmonics of the sample-clock frequency, and these harmonics may introduce into the read channel noise that increases the data-recovery error rate of the read channel.
In contrast, a digital-synchronizing data-communications system effectively, but not actually, shifts the phase and frequency of a free-running sample clock to respectively match the phase and frequency of data that the read signal is carrying that is free running at the expected frequency of the data.
In this type of system, the read channel may include a phase-acquisition (PA) loop for acquiring the phase difference between the data and the sample clock, and may include an interpolated-timing-recovery (ITR) circuit, which, in response to the acquired phase difference, effectively shifts the phase and frequency of the free-running sample clock to respectively match the phase and frequency of the data. Specifically, the ITR circuit alters the phase of an actual sample of the data signal such that the altered sample has substantially the same magnitude/phase that the actual sample would have had if the sample clock had been synchronized to the data. Furthermore, if the frequency of the sample clock is less than twice the frequency of the data—this is an under-sampling condition where the read channel periodically generates fewer than two samples during a period of the data—then the ITR circuit may compensate by periodically processing a sample twice. Conversely, if the frequency of the sample clock is greater than twice the frequency of the data—this is an over-sampling condition where the read channel periodically generates more than two samples during a period of the data—then the ITR circuit may compensate by periodically processing an extra sample simultaneously with the normally processed sample(s).
As discussed in more detail below, a potential problem with a digital-synchronizing data-communications system is that the PA loop of the read channel may limit the amount of data that the read channel can process during a given time period or that one can store in a storage medium of a given size. The PA loop is often relatively slow, and thus may take a relatively long time to acquire the phase difference between the data and the sample clock, particularly where the data has a different frequency than the sample clock. Because the PA typically acquires the phase difference during the preamble of the read signal, the preamble may be relatively long to accommodate the slow speed of the PA loop. Unfortunately, the longer the preamble, the less data that the read channel can process during a given period for a data-communications system such as a cell phone, and the less data that one can store in a fixed-size storage medium, such as a magnetic disk, that the read channel reads.
Furthermore, in a digital-synchronizing data-communications system, the read channel may include a gain-acquisition (GA) loop for acquiring the gain of the read channel that sets the amplitude of the read signal to a desired level.
As discussed in more detail below, another potential problem with a digital-synchronizing data-communications system is that it like the PA loop, the GA loop of the read channel may limit the amount of data that the read channel can process during a given time period or that one can store in a storage medium of a given size. Like the PA loop, the GA loop is often relatively slow, and thus may take a relatively long time to acquire the proper gain for the read channel. Because the GA loop typically acquires the gain during the preamble of the read signal, the preamble may be relatively long to accommodate the slow speed of the GA loop. Unfortunately, as discussed above, the longer the preamble, the less data that the read channel can process during a given period and the less data that one can store on a fixed-size storage medium that the read channel reads.
Also as discussed in more detail below, another potential problem with a digital-synchronizing data-communications system is that there is little flexibility in locating the variable-gain stage used to adjust the gain of the read channel. Typically, the variable-gain stage is an analog variable-gain amplifier, which thus must be placed in front of the channel's analog-to-digital converter (ADC). Consequently, one cannot locate the variable-gain stage in back of the ADC even if such a location may be desired in a particular application.
The following is a brief overview of the operation of the PA loop and the ITR circuit during the preamble of the read signal.
FIG. 1 is a timing diagram of a sinusoidal preamble 10 of a read signal, a sample clock 12 that is synchronized to the preamble, and a sample clock 14 that has the same frequency as but is out of phase with the preamble. The preamble has a peak-to-peak amplitude of 2 (−1 to +1).
Referring to the synchronized sample clock 12, the rising edges 16 are aligned with the peaks 18 of the preamble 10, and the falling edges 20 are aligned with the zero crossings 22 of the preamble. That is, the rising edges 16 sequentially generate alternating sample values “+1” and “−1”, and the falling edges 20 generate sample values “0”. The preamble peaks 18 and zero crossings 22 correspond to the preferred times for the sample clock 12 to sample the subsequent data portion (not shown) of the read signal. Therefore, because the sample clock 12 is synchronized with the preamble 10, it will also be synchronized to the data portion of the read signal.
In contrast, referring to the unsynchronized sample clock 14, which lags the synchronized sample clock 12 by 180° in this example, the rising edges 24 of the unsynchronized sample clock are aligned with the zero crossings 22 of the preamble 10, and the falling edges 26 are aligned with the peaks 18 of the preamble. That is, the rising edges of 24 generate sample values “0”, and the falling edges 26 sequentially generate alternating sample values “+1” and “−1”.
Consequently, if the system sample clock has the same phase as the unsynchronized sample clock 14, then the PA loop of the read channel acquires the phase difference of −90° (a phase lag) between the sample clock and the preamble 10 during a phase-acquisition period T sync—the phase difference is −90°, not 180°, because the frequency of the preamble sinusoid is half that of the sample clock. Furthermore, although not shown in FIG. 1, if the sample clock has a different frequency than the preamble 10, then the phase difference will not be constant, but will change from sample to sample. But because phase is merely the integral of frequency, one can track the frequency difference over time by tracking the phase difference over time.
In response to this acquired phase difference of −90°, the ITR circuit effectively shifts the phase of the sample clock 14 by +90° relative to the preamble 10 by sequentially generating adjusted sample values of “−1” and “+1” for alternating actual sample values of “0” generated at the rising edges 24, and by generating an adjusted sample value of “0” for each actual sample value of “−1” and “+1” generated at the falling edges 26.
The following is a more detailed discussion of a PA loop, and a discussion of a GA loop.
FIGS. 2A and 2B are a block diagram of a conventional read channel 30 for a disk drive. FIG. 2A shows a data path 32 and a PA loop 34 of the read channel 30, and FIG. 2B shows the data path and a GA loop 36 of the read channel. Although not shown, a sample clock, such as the sample clock 12 or the sample clock 14 of FIG. 1, drives each of the illustrated components of the read channel 30.
Referring to FIGS. 2A-2B, the data path 32 includes a front end 38, an ITR circuit 40, a finite-impulse-response (FIR) filter 42, and a Viterbi detector 44. The data path 32 may generate and process one or more samples of the read signal at a time. For example, a half-rate data path 32 generates and processes two samples of the read signal during each period of the sample clock.
The front end 38 includes a read head and pre-amplifier 46, a variable-gain amplifier (VGA) 48, and an analog-to-digital converter (ADC) 50. The read head and pre-amplifier 46 convert the data and other information stored on the disk (not shown in FIGS. 2A and 2B) into an analog read signal, and the VGA 48 adjusts the amplitude of the analog read signal to a predetermined value or range of values deemed suitable for the subsequent components of the data path 32. The ADC 50 samples the gain-adjusted analog read signal in response to the sample clock (not shown in FIGS. 2A and 2B), and thus converts the analog read signal into a digital read signal.
As discussed above, the ITR circuit 40 adjusts the values of the samples from the ADC 48 to correct for a nonzero phase difference between the sample clock and the data, and also manipulates the samples as needed to compensate for under sampling or over sampling. An example of an ITR circuit that may be the same as or similar to the ITR circuit 40 is disclosed in U.S. Pat. No. 6,556,633 and U.S. Publication No. 2002/0067781, which are incorporated by reference.
The FIR 42 equalizes the phase-corrected and sampling-rate-compensated samples from the ITR circuit 40 to a time-domain waveform that corresponds to target polynomial (e.g., PR4, EPR4, E2PR4) that represents or approximates the frequency response of the data stored on the disk (not shown in FIGS. 2A and 2B).
The Viterbi detector 44 recovers the stored data from the equalized samples of the read signal received from the FIR 42. An example of a Viterbi detector that may be the same as or similar to the Viterbi 44 is disclosed in U.S. Pat. No. 6,662,338 and U.S. Publication Nos. 2004/0010749 and 2004/0010748, which are incorporated by reference.
Referring to FIG. 2A, in addition to the ITR 40 and the FIR 42, the PA loop 34 includes a pattern generator (PGEN) 52, a multiplexer (MUX) 54, an ideal sample generator (ISG) 56, a delay circuit 58, a phase detector 60, a proportional-integral filter (PIF) 62, a phase-correction value (T) accumulator 64, and a zero-phase-restart (ZPR) circuit 66. The phase-correction value T effectively equals the complement of the phase difference between the sample clock and the data, and is the amount by which the ITR 40 effectively shifts the phase of the sample clock to synchronize the sample clock to the data. Therefore, the PA loop 34 effectively acquires the phase difference (sometimes abbreviated to only “phase”) between the sample clock and the data by acquiring the phase-correction value T. Similarly, a phase tracking (PT) loop, which is described below, effectively tracks the phase between the sample clock and the data by tracking T.
The PGEN 52 receives from the ZPR 66 an initial value of the phase-correction value T between the preamble sinusoid and the sample clock (FIG. 1), and, in response to the initial value of T, generates a value that represents the point (0, +1, −1) of the preamble that the sample clock would have caused the ADC 50 to sample if the initial phase difference, and thus the initial value of T were both equal to zero.
The MUX 54 couples the input of the ISG 56 to the output of the PGEN 52 during acquisition of the phase-correction value T (which, as discussed above, is the complement of the phase difference between the read signal and the sample clock), and couples the input of the ISG 56 to the output of the Viterbi detector 44 during tracking of T—the phase-correction value T is maintained, i.e., tracked, after the PA loop 34 acquires T as discussed below.
The ISG 56 generates an ideal sample value that is based on the value from the PGEN 52 during phase acquisition, and that is based on the recovered data from the Viterbi detector 44 during phase tracking. The ideal sample value is the value that a sample would have assuming that, e.g., the phase difference, and thus the phase-correction value T, equals 0, no noise is present on the read signal while the sample is generated, and the gain of the VGA 48 is such that the amplitude of the read signal has a predetermined value.
The delay circuit 58 provides that both inputs to the phase detector 60 correspond to the same sample of the read signal. Specifically, during acquisition of the phase-correction value T, the delay circuit 58 delays a sample output from the FIR 42 by a time substantially equal to the time required for the PGEN 52 to generate a value, for the value to propagate through the MUX 54, and for the ISG 56 to generate a corresponding ideal sample value. And during tracking of the phase-correction value T, the delay circuit 58 delays a sample output from the FIR 42 by a time substantially equal to the time required for the Viterbi detector 44 to generate a data value, for the value to propagate through the MUX 54, and for the ISG 56 to generate a corresponding ideal sample value. Therefore, the delay circuit 58 may have different delay times during phase acquisition and phase tracking.
The phase detector 60 compares the value of the delayed FIR sample from the delay circuit 58 with the ideal sample value from the ISG 56, and from the difference between these two values determines a raw phase difference between the read signal and the sample clock.
The PIF 62 filters high-frequency noise and other high-frequency artifacts such as jitter from the raw phase difference received from the phase detector 60 to generate an error signal. More specifically, the PIF 62 includes two paths or portions that are not shown in FIG. 2A: an integrator portion, sometimes called the frequency accumulator, that integrates the error signal to generate a frequency-correction component of the phase-correction value T, and a proportional portion that generates from the error signal an instantaneous-phase-correction component of T.
The accumulator 64 stores the phase-correction value T, and increments or decrements T in proportion to the magnitude and polarity of the error signal from the PIF 62.
The ZPR circuit 66 exploits the sinusoidal form of the read-signal preamble (FIG. 1) to generate and provide to the accumulator 64 and to the PGEN 52 an initial value of the phase-correction value T during the acquisition of T by the PEA loop 34. By providing an initial value of T, the ZPR circuit 66 may significantly reduce the time that the PA loop 34 requires to acquire T. Examples of ZPR circuits that may be the same as or similar to the ZPR circuit 66 are disclosed in U.S. Pat. Nos. 6,775,084 and 6,366,225, which are incorporated by reference.
Still referring to FIG. 2A, the operation of the PA loop 34 is discussed. Generally, the PA loop 34 acquires the phase of the sample clock relative to the data. That is, the PA loop 34 determines the error, i.e., difference, between the phases of the sample clock and data, and generates a phase-correction value T, which the ITR 40 uses to effectively reduce this phase difference.
In response to a read-data-sector command from the computer or other system (not shown in FIGS. 2A and 2B) in which the read channel 30 is incorporated, the front end 38 begins reading and generating samples of the sinusoidal preamble (FIG. 1), which is located at the beginning of the data sector (not shown in FIGS. 2A and 2B) being read. As discussed below in conjunction with FIG. 2B, the GA loop 36 begins to set the gain of the VGA 48 to a suitable value. For purposes of explanation of the PA loop 34, it is assumed that at all times the VGA 48 has a gain suitable for proper operation of the PA loop. This assumption is typically valid as discussed below in conjunction with FIGS. 2B-3.
The ZPR circuit 66 determines an initial phase difference between the sample clock and the sinusoidal preamble from the ADC 50, and from the initial phase difference calculates an initial value of the phase-correction value T using the first n samples of the preamble. For example, n may range from 8-24 samples.
Next, the ZPR circuit 66 loads the initial value of the phase-correction value T into the T accumulator 64 and into the PGEN 52.
Then, in response to the initial value of T, the PGEN 52 generates a PGEN value representing the in-phase sample value (−1, 0, or +1) of the preamble for the current period of the sample clock, and the MUX 54 provides this value to the ISG 56.
Next, the ISG 56 generates the ideal value (−1, 0, or +1) of the in-phase sample represented by the PGEN value, and provides this ideal sample value to the phase detector 60.
Concurrently with the above-described operations of the PGEN 52, MUX 54, and ISG 56, the delay circuit 58 provides to the phase detector 60 the actual sample value from the FIR 42, where the actual sample value is the actual value of the same sample to which the ideal sample value from the ISG 56 corresponds.
Then, the phase detector 60 determines the difference between the actual and ideal sample values from the delay circuit 58 and the ISG 56, respectively, and from this difference calculates a raw phase difference between the sample clock and the data that the read signal is carrying.
Next, the PIF 62 generates an error signal in response to the raw phase difference from the phase detector 60. The frequency response of the PIF 62 is designed to stabilize the PA loop 34 so that the PA loop has a desired transient response and does not oscillate.
Then, in response to the error signal from the PIF 62, the accumulator 64 adjusts the value T in the accumulator.
The PA loop 34 operates in this iterative fashion for subsequent samples of the preamble until the phase-correction value T in the accumulator 64 converges substantially to the value that corresponds to the actual phase difference between the sample clock and the data that the read signal is carrying.
After the PA loop 34 acquires the phase-correction value T during the preamble portion of the read signal, a phase tracking (PT) loop maintains T substantially equal to the value that corresponds to the actual phase difference between the sample clock and the data during the data portion of the read signal—although not outlined in FIG. 2A, the PT loop is the same as the PA loop 34 except that the PT loop includes the Viterbi detector 44 and lacks the PGEN 52 and the ZPR circuit 66 during tracking of T. The PT loop operates similarly to the PA loop 34, except that the ZPR circuit 66 is inactive and the MUX 54 provides the output of the Viterbi detector 44, not the output of the PGEN 52, to the ISG 56. During the data portion of the read signal, the read signal may no longer be sinusoidal. Consequently, the ISG 56 calculates the ideal sample values using data from the Viterbi detector 44 and the target polynomial according to which the FIR 42 equalizes the samples of the read signal.
Still referring to FIG. 2A, it has been estimated that where the read channel 30 generates and processes two samples of the read signal per period of the sample clock, the PA loop 34 requires approximately 118-154 samples of the sinusoidal preamble to acquire the phase-correction value T for a worst-case frequency error of 0.4% between the sample clock and the data. Specifically, where the latency of the PA loop 34 (the number of periods of the sample clock required for a signal to propagate from any point of the loop back to that point) is 15 periods of the sample clock, then, to acquire T under a worst-case condition, it is estimated that the PA loop requires Tsync (FIG. 1) to include approximately 118-134 samples of the preamble sinusoid (110 samples of the preamble subsequent and in addition to the 8-24 samples that the ZPR circuit 66 requires to generate an initial value for T). And where the latency of the PA loop 34 is 17 periods of the sample clock, then, to acquire T under a worst-case condition, it is estimated that the PA loop requires Tsync to include approximately 138-154 samples of the preamble (130 samples of the preamble subsequent and in addition to the 8-24 samples that the ZPR circuit 66 requires to generate an initial value for T).
Unfortunately, as stated above, the longer the preambles of the data sectors, the less data that one can store on a disk of a given storage capacity. For example, if a disk includes one million data sectors, then every eight samples that the preamble provides reduces the data-storage capacity of the disk by 1 Megabyte (MB).
Referring to FIG. 2B, in addition to the ITR 40, the FIR 42, the PGEN 52, the MUX 54, the ISG 56, and the delay circuit 58, the GA loop 36 includes the VGA 48, the ADC 50, a zero-gain-restart (ZGR) circuit 68, and a gain controller 70.
The ZGR circuit 68 exploits the sinusoidal form of the preamble (FIG. 1) to generate and provide to the gain controller 70 an initial gain-correction (GC) value corresponding to the difference between the predetermined desired amplitude and the amplitude of the digital read signal from the ADC 50. By providing an initial value of the GC value, the ZGR circuit 68 may significantly reduce the time that the GA loop 36 requires to acquire the VGA gain that causes the read signal to have the desired amplitude. Examples of ZGR circuits that may be the same as or similar to the ZGR circuit 68 are disclosed in U.S. patent application Ser. Nos. 09/503,949 and 09/503,399, which are incorporated by reference.
FIG. 3 is a schematic diagram of the gain controller 70 and the VGA 48 of FIG. 2A. The gain controller 70 generates a gain-control (GC) signal—the GC signal may be analog or digital—value based on the difference between the ideal and actual sample values from the ISG 56 and the delay circuit 58, and provides the GC signal to the VGA 48; the GC signal causes the VGA to impart the desired amplitude to the read signal.
The gain controller 70 includes a comparator 72, which calculates the difference between the ideal and actual sample values, and an amplifier 74, which has a fixed gain K over a predetermined bandwidth and which amplifies the difference to generate an error signal. The combination of the comparator 72 and the amplifier 74 may be referred to as a comparator circuit. The gain controller 70 also includes an accumulator 76, which stores the GC value from which the accumulator (or other circuitry such as a digital-to-analog converter (DAC) (not shown)) generates the GC signal. For example, where the GC signal is a digital signal, the GC signal may equal the GC value. Initially, the accumulator 76 stores the initial GC value from the ZGR 68 (FIG. 2). The gain controller 70 further includes an adder 78, which updates the GC value in the accumulator 76 in response to the error signal from the amplifier 74. The combination of the accumulator 76 and the adder 78 may be referred to as an accumulator circuit.
Referring to FIGS. 2B-3, the operation of the GA loop 36 is discussed.
In response to a read-data-sector command from the computer or other system (not shown in FIGS. 2A-3) in which the read channel 30 is incorporated, the front end 38 begins reading and generating samples of the sinusoidal preamble (FIG. 1), which is located at the beginning of the data sector (not shown in FIGS. 2A-3) being read. As discussed above in conjunction with FIG. 2A, the GA loop 36 begins to set the gain of the VGA 48 to a suitable value. For purpose of explanation of the GA loop 36, it is assumed that at all times the phase-correction value accumulator 64 (FIG. 2A) provides a value of T suitable for proper operation of the GA loop. This assumption is typically valid, because the ZPR 66 and the ZGR 68 operate independently of one another, and the initial values provided by the ZPR and ZGR typically allow the interdependent PA and GA loops 34 and 36 to operate properly.
The ZGR circuit 68 determines an initial value of the difference between the desired amplitude and the actual amplitude of the sinusoidal preamble read signal using the first n samples of the sinusoidal preamble from the ADC 50, and from this value generates an initial GC value. For example, n may range from 8-24 samples.
Next, the ZGR circuit 68 loads the initial GC value into the accumulator 76, which provides to the VGA 48 an initial GC signal based on this initial GC value.
Then, the PGEN 52, MUX 54, ISG 56, and delay circuit 58 operate as discussed above in conjunction with the operation of the PA loop 34 of FIG. 2A. The ideal sample value from the ISG 56 has a value that represents the ideal amplitude of the actual sample at the output of the FIR 42.
Next, the comparator 72 determines the difference between the actual and ideal sample values from the delay circuit 58 and the ISG 56, respectively, and provides this difference to the amplifier 74.
Then, the amplifier 74 amplifies the difference from the comparator 72 to generate the read-signal-amplitude error signal, and provides this gain error signal to the adder 78.
Next, in response to the error signal from the amplifier 74, the adder 78 adjusts the GC value in the accumulator 76 in proportion to the magnitude and polarity of the error signal.
The GA loop 36 operates in this iterative fashion for subsequent samples of the preamble until the GC value in the accumulator 76 converges to a value that causes the read signal in the data path 32 to have substantially the desired amplitude.
After the GA loop 36 acquires the GC value during the preamble portion of the read signal, a gain-tracking (GT) loop maintains the GC value at an appropriate value—although not outlined in FIG. 2B, the GT loop is the same as the GA loop 34 except that the GT loop includes the Viterbi detector 44 and lacks the PGEN 52 and the ZGR circuit 68. During tracking of the GC value, the GT loop operates similarly to the GA loop to maintain the amplitude of the read signal at a desired level, except that the ZGR circuit 68 is inactive and the MUX 54 provides the output of the Viterbi detector 44, not the output of the PGEN 52, to the ISG 56. Consequently, as discussed above in conjunction with the PA loop 34 of FIG. 2A, the ISG 56 calculates the ideal sample values using the recovered data from the Viterbi detector 44 and the target polynomial according to which the FIR 42 equalizes the samples of the read signal.
Referring to FIG. 2B, because the analog VGA 48 must be located in front of the ADC 50, the GA loop 36 has a relatively large latency, and thus requires a relatively large number of samples of the preamble to accurately acquire the GC value that results in the desired amplitude for the read signal. The location of the VGA 48 in front of the ADC 50 may also cause other problems, such as saturation of the ITR 40, FIR 42, or Viterbi detector 44—saturation occurs when the amplitude of a signal input to or output from a circuit exceeds the circuit's input or output amplitude range.
Unfortunately, as discussed above in conjunction with the PA loop 34 of FIG. 2A, the longer the preambles of the data sectors, the less data that one can store on a disk of a given storage capacity.
Moreover, because the VGA 48 is in front of the ADC 50, the GA loop 36 and the GT loop both encompass the digital portion of the read channel 30 (the portion in back of the ADC) and the analog front end 38 of the read channel.
Unfortunately, it may be desirable for the GA loop 36 and the GT loop to be located entirely within the digital portion of the read channel 30.